What is contained on an integrated circuit?

Recycling of Tickets and Passes

It is necessary to buy a ticket or a commuter pass to ride a train, but these are finally disposed of as trash.

However, the IC card tickets released in 2001 can be repeatedly used and contribute to a considerable saving of resources. Recently, the IC card tickets have become popular around urban areas, and one can use trains of different companies with one IC card ticket, which substantially contributes to reducing the resource consumed. To prevent the IC card from being disposed, a deposit system is used.

JR East introduced the IC card ticket ‘Suica’ in November 2001 as a new ticket that replaces a magnetic commuter pass. As a result, the number of annually issued magnetic commuter passes decreased by approximately 17,100,000 in 2006 compared with the number in 2000, which was the year immediately before Suica was introduced.

However, almost 100% of the collected large quantities of used tickets and magnetic commuter passes are recycled. Iron powder on the backside of these tickets is separated, and the paper is recycled as toilet paper, corrugated cardboard, and business cards.

I Introduction

A modern integrated circuit is a complex three-dimensional structure of alternating, patterned layers of conductors, dielectrics, and semiconductor films. This structure is fabricated on an ultrahigh-purity wafer substrate of a semiconducting material such as silicon. The performance of the device is, to a large degree, governed by the size of the individual elements. As a general rule, the smaller the elements, the higher the device performance will be. The structure is produced by a series of steps used to precisely pattern each layer. The patterns are formed by lithographic processes that consist of two steps: (1) delineation of the patterns in a radiation sensitive thin-polymer film called the resist, and (2) transfer of that pattern using an appropriate etching technique. A schematic representation of the lithographic process is shown in Fig. 2.2 Materials that undergo reactions that increase their solubility in a given solvent (developer) are called positive-tone resists, while those that decrease their solubility are known as negative-acting materials. The focus of this review concerns the design and selection of polymer materials that are useful as radiation-sensitive resist films. Such polymers must be carefully designed to meet the specific requirements of each lithographic technology and device process.

An overwhelming preponderance of devices continues to be fabricated via “conventional photolithography” employing 350 to 450 nm light. Incremental improvements in tool design and performance with concomitant refinements in the novolac/diazonaphthoquinone resist materials chemistry and processing have allowed the continued use of this technology to produce ever-smaller features (Table I). The cost of introducing a new technology, which includes the costs associated with the development and implementation of new hardware and resist materials, is a strong driving force pushing photolithography to its absolute resolution limit and extending its commercial viability.3

TABLE I. Evolution of Lithographic and Semiconductor Device Technologies

The technological alternatives to conventional photolithography are largely the same as they were a decade ago: short-wavelength (>250 nm) photolithography, scanning or projection electron-beam, X-ray or EUV, or ion-beam lithography.2,4 Unfortunately, conventional photoresists are not appropriate for use with these new, alternative lithographic technologies. The most notable deficiencies of these materials are their inherent low sensitivity and absorption characteristics that are too high for shorter wavelength exposure to allow uniform imaging through practical resist film thicknesses (about 0.5 to 1 μm). Thus, no matter which technology becomes dominant after photolithography has reached its resolution limit, new resists and processes will be required.5 The introduction of new resist materials and processes will also require considerable lead time to bring them to the performance level currently realized by conventional positive photoresists.

There are significant trade-offs between optimum process performance and the chemical design of new resists. The ultimate goal of any lithographic technology is to be able to produce the smallest possible features with the lowest cost per level and with wide process latitude. The best solution will invariably require compromises, and an understanding of materials and process issues is essential to select the correct compromise.

6.1.3 The ASIC design flows

Nowadays, the design flow of ASIC has been highly automated. The automation tools provide reasonable performance and cost advantage over manual design processes. Broadly, ASIC design flow can be divided into the phases given below in this subsection, which are also illustrated in Figure 6.3.

Designing a programmable-logic or application-specific IC involves many different tasks, some carried out by the ASIC designers, while others are taken care of by the ASIC vendor. Since a digital ASIC cannot be changed once it is manufactured, verification of its functions is crucial before the masks for production are made. Therefore, considerable effort is needed to simulate the design at different levels to verify that no bugs exist. The ASIC design is described using a hardware description language, HDL. There are a number of such languages available, such as Verilog, VHDL, System C or System Verilog. The language can describe the hardware at different levels of detail. The most common level used today is called register transfer level, RTL. This level describes the functions of the ASIC with logic relations between memory elements (registers).

Simulation is a key step for the programmed functions to verify their correctness, but they also need to be translated into hardware, i.e. logic gates. This is called synthesis and is done using software tools. The result of the synthesis must be verified, both from a functional and a timing perspective. This is done by gate-level simulations, or by comparing the logic produced by synthesis to the programmed functions in the HDL. The latter is called formal verification or equivalence check. A floorplan/layout tool places the logic gates on a model of the physical ASIC. This enables the calculation of signal delays between all logic elements.

Due to an increase in signal speed, miniaturization of features, smaller chip sizes, and lower power supply voltages, interconnect signal integrity problems have increased. Signal delay due to interconnect delay is more significant than gate delay. As a result, more powerful automation tools are required for layout parameter extraction, timing delay and crosstalk simulation, and power analysis. Static timing analysis (STA) is also used to constrain the layout tools and to verify that the design will work at the specified frequency. When the ASICs are manufactured, each chip needs to be tested in order to ensure that all delivered devices work properly.

The ASICs are tested using test vectors; either functional vectors or automatically generated vectors, or both. Functional vectors apply signals to the ASIC which are similar to the signals that the ASIC would receive in a real environment. Automatically generated vectors, on the other hand, only apply signals to verify that no defects exist within the ASIC, without relating to how the ASIC will be used in its target environment. This area of work is called design for test.

To gain better understanding of the ASIC design flow, design issues for the standard cell are taken as an example, and discussed in the following paragraphs. Usually, the initial design of a standard cell is developed at the transistor level, in the form a transistor netlist. This is a nodal description of transistors, of their connections to each other, and their terminals (ports) to the external environment. Designers use computer-aided design (CAD) programs to simulate the electronic behavior of the netlist, by declaring input stimulus (voltage or current waveforms) and then calculating the circuit’s time domain (analogue) response. The simulations verify whether the netlist implements the requested function, and predict other pertinent parameters such as power consumption or signal propagation delay. Figure 6.4 is a physical design flow for standard-cell ASIC.

Standard-cell ICs are designed in the following conceptual steps (or flow), although they overlap significantly in practice. These steps, implemented with the level of skill common in the industry, almost always produce a final device that correctly implements the original design, unless flaws are later introduced by the physical fabrication process.

The design engineers start with a non-formal understanding of the required functions for a new ASIC, usually based on a customer requirements analysis.

The design engineers construct a specification of an ASIC to achieve these goals using an HDL. This is usually called the RTL (register transfer level) design.

Suitability for purpose is verified by functional verification. This may include such techniques as logic simulation, formal verification, emulation, or creating an equivalent pure software model.

Logic synthesis transforms the RTL design into a large collection of lower-level constructs called standard cells. These constructs are taken from a standard-cell library consisting of precharacterized collections of gates. The standard cells are typically specific to the intended manufacturer of the ASIC. The resulting collection of standard cells, plus the necessary electrical connections between them, is called a gate-level netlist.

The gate-level netlist is next processed by a placement tool which places the standard cells onto a region representing the final ASIC. It attempts to find a placement of the standard cells, subject to a variety of specified constraints.

The routing tool takes the physical placement of the standard cells and uses the netlist to create the electrical connections between them. The output is a file which can be used to create a set of photo-masks enabling a semiconductor fabrication facility to produce physical ICs.

Given the final layout, circuit extraction computes the parasitic resistances and capacitances. In the case of a digital circuit, this will then be further mapped into delay information, from which the circuit performance can be estimated, usually by static timing analysis. This and other final tests, such as design rule checking and power analysis (collectively called signoff), are intended to ensure that the device will function correctly over all extremes of the process, voltage and temperature. When this testing is complete the photo-mask information is released for chip fabrication.

These design steps (or flow) are also common to standard product design. The significant difference is that the latter uses the manufacturer’s cell libraries that have been used in potentially hundreds of other design implementations, and therefore are of much lower risk than full custom design. Standard cells produce a cost-effective, design density and they can also integrate IP cores and SRAM (static random access memory) effectively, unlike gate arrays.

Waste

Water usage in integrated circuit manufacture is among the highest in any industrial sector. The process requires large quantities of deionized water. Because of the purity required, process water is not recycled, and hence wastewater discharge is a major issue. Current use of ultrapure water (UPW) is 5 to 7 L/cm2 of silicon, and in a wet bench, it is 53 L/wafer (300 mm). This works out to 20.45 million tons of water for producing 2.7 billion square centimeters of wafer. The semiconductor fabricators that use chemical mechanical planarization/polishing (CMP) consume 4.2 to 12 gallons of water per minute, which works out to more than 4.25 million gallons annually. Thus, at an average cost of $0,016 per gallon of UPW and the same amount for subsequent average waste disposal, operating a single polisher requires an expenditure of $136,000 per year in water-related costs alone.

From Figs. 14-1 to 14-3 one can see that unreacted highly toxic metals, liquids, and gases could be leaving the semiconductor manufacturing plant as waste. Hydrofluoric acid is the major inorganic acid present in the gaseous effluent stream, and calcium fluoride is also generated at 0.0018 kg per square centimeter of wafer (2000 data). Fumes from lead soldering, tin plating, and other vaporized metals used in the chemical vapor deposition also escape with the effluent gases. Disposal of these hazardous effluents such as waste solvents, dissolved organic compounds, acids, alkalis, photoresistant chemicals, dissolved metals (including arsenic, copper, chromium, and selenium), waste etchants, waste aqueous developing materials, and catalyst solutions pose a major problem. Chlorofluorocarbons (CFCs), halons, carbon tetrachloride, and polychlorinated biphenyls have been banned or voluntarily phased out from the manufacturing process. Lead, cadmium, and mercury compounds used in packaging substrates, and perfluoro octyl sulfonates (PFOS), a component in some photoresists and antireflective coatings, have been grouped under the high-risk category (chemicals or materials have been targeted by a government authority for significant use restriction or potential ban). Perfluorocarbons (PFCs) and hydrofluorocarbons (HFCs), both of which have high global warming potential but shorter atmospheric lifetimes than the CFCs, have been grouped under the medium-risk chemicals (significant regulation of these compounds).

The manufacture of compound semiconductors such as gallium arsenide, indium phosphide, and indium antimonide require the use of a number of very hazardous gases, which include arsine, phosphine, trimethyl indium, trimethyl gallium, trimethyl aluminum, silane, and others. Disposal of unconsumed process gases and the products of the deposition process pose several problems. The worst long-term environmental concern among these is arsine, which will always produce an arsenic-tainted waste stream. In addition, the presence of phosphorous and hydrogen during pumping could also lead to pyrophoric conditions.

Current use of ultrapure water (UPW) is 5 to 7 L/em2 of silicon, and the goal is to reduce this level to 4 to 6 L /cm2 by 2005. UPW use in a wet bench is 53 L/wafer (300 mm), which should be reduced to 43 L/wafer by 2005. The chemical use target is to reduce the quantity (in liters per square centimeter per mask layer) by 5% per year via more efficient use, recycle, and reuse systems. Reuse of wastewater (for cooling towers, for instance) should increase from current average levels of 65 to 70% in 2005, 80% in 2010, and 90% in 2013. Energy use for all fabrication tools is 0.5 to 0.7 kWh/cm2, which should be brought to 0.4 to 0.5 kWh/cm2 in 2005 and 0.3 to 0.4 kWh/cm2 in 2008. By 2010, PFC emissions must be reduced by 10% from the 1995 baseline, as agreed to by the World Semiconductor Council. Through process optimization and alternative chemistries, recycling, and/or abatement, the industry must continue to diminish the emissions of byproducts with high global warming potential. The estimated cost to the United Kingdom economy could be as much as $761 million a year for complying with the “Waste Electrical and Electronic Equipment Directive” (European Commission 2002/95/EC and 2002/96/EC). A further $334 million a year might be needed by the industry to meet “Restriction of Use of Certain Hazardous Substances.” Possible use of supercritical CO2 for cleaning instead of water is being investigated to reduce water usage. Sulfur trioxide is being tried instead of wet chemicals as a cleaning agent for removing residual photoresist and organic polymers. This attempt could reduce the handling of large quantities of hazardous chemicals.

18.6.3 Temperature sensor

Temperature sensor is an integrated circuit sensor. The output voltage is linearly proportional to the centigrade temperature. The sensor shown in figure is compatible with Arduino UNO device. The applications of the temperature sensor are in microwave ovens, fridges, household devices, air conditioners, and atmosphere and water temperature monitoring. It can measure not only the hot bodies but also cold bodies. There are two types of sensors, they are noncontact temperature sensors and contact temperature sensors. Contact temperature sensors are again divided into three subtypes: electromechanical, resistive resistance temperature detectors, and semiconductor-based temperature sensors (Fig. 18.5).

4.3 Microfabrication Techniques for Engineering Materials

Fabrication techniques developed for integrated circuit (IC) production have been refined to the extent of supporting a multi-billion-dollar industry. Chip manufacturing relies on silicon-based processing where micron-sized features are routinely used in production. MECS do not require the extremely small “line widths” needed for IC fabrication. Furthermore, in many energy applications, silicon is not the favored material, as discussed previously. Other fabrication techniques, such as LIGA, have been specifically developed for MEMS. Although many rely heavily on silicon processing, others can produce very small structures in metals electrodeposited on a surface or within a micromold. Again, for MECS applications, the feature size of these MEMS fabrication techniques is usually much smaller than what is needed.

Because MECS are fundamentally different from traditional ICs and MEMS, they require different materials and fabrication processes. One important fabrication method for microenergy applications is called microlamination or platelet technology (Fig. 5). Although its history dates back to the 1970s, when it was developed for liquid rocket engine injectors, it is now being pursued by a number of groups for fabricating MECS. The method is based on microlamination of metals, ceramics, and polymers. The process begins by surface machining, or cutting, a single lamina with a pattern containing the desired structure. The lamina is often a shim of a material having desirable mechanical and thermal properties important to the functioning of the final device. Once the pattern is cut, the shims are surface treated and precisely stacked in a prearranged order. The stack is then bonded together, forming a single block of material. For the platelet architecture to have utility, a machining method capable of fabricating structures in the laminating material is needed. The method must be versatile, easy to use, and capable of rapid machining (with through-cuts and surface texturing) in a wide variety of materials. One of the most general techniques is laser numerically controlled micromachining. It is most useful for prototype runs and can be used on metals and polymers. Other useful techniques specific to only one class of material can also be used. For example, chemical etching through a photographically defined mask (photolithography) can be used on most metals. The process is commercially available and can be employed for high-volume production runs. Another machining technique applicable to most metals is wire-based electro-discharge machining (wire EDM). Current machines on the market are numerically controlled and have wire diameters as small as 50 μm. The cutting of metal platelets with this technique is primarily a two-dimensional operation and can be as precise at 5 μm. Note that conventional high-speed milling, with end mills as small as 100 μm, can be achieved with most modern equipment and can be applied to both metals and plastics. Although wire EDM and conventional milling with small tools have been described in the context of platelet fabrication, their precision and speed can also be applied to a wide range of small mechanical components needed for MECS.

The properties of ceramics (and of materials such as quartz) are desirable from an energy systems point of view, but this class of material is difficult to machine and form. Relatively few techniques are available for cutting the requisite structures in ceramics. However, work is progressing on various additive techniques for making small components out of both plastics and ceramics. Some of these techniques go by the name stereolithography and often employ a laser to selectively fuse a particle bed of the starting material into a desired shape.

VI Diffusion

The transistors in an integrated circuit consist of small regions doped with different amounts of various impurities to produce p-n junctions. There are several ways in which a desired local variation in impurity content can be produced: by ion implantation, by growth of a new layer of crystal doped differently from the substrate, and by diffusion of an impurity.

Imagine that we have a wafer of silicon doped uniformly with boron at a concentration of 1016 boron atoms per cm3 of silicon. Boron is an acceptor, making the silicon p-type. To produce a p-n junction we can diffuse a donor impurity such as phosphorus in from the surface by heating the silicon in a gas containing elemental phosphorus or a phosphorus compound. The p-n junction is the surface in the crystal where the boron and phosphorus concentrations are equal. If the boron concentration remains at its original value of 1016/cm3 throughout the crystal, then the p-n junction is at the point where the phosphorus concentration is also 1016/cm3. The spatial distribution of two impurities near the junction determines the electrical characteristics of the device.

Diffusion is carried out in resistance-heated tube furnaces like those used for oxidation. Usually a gaseous diffusion source is passed through the tube. Typical gases are BBr3, B2H6, PH3, AsH3, POCl3, B(CH3O)3, BCl3, PBr3, and Sb3Cl5 in a carrier gas such as H2, He, or O2. Alternatively, wafers may be exposed to ampules with diffusion sources, a liquid diffusant may be applied on the wafers, or a solid source may be used from which the impurity evaporates. Usually O2 is used as a carrier gas so that oxidation takes place at the same time as impurity diffusion, simultaneously preparing the wafers for the next lithographic step. The presence of oxygen also prevents halide diffusion sources from roughening the surface of the silicon by etching.

If the diffusion coefficient D for the impurity in the silicon is constant, if the concentration Cs of impurity at the surface of the wafer is constant, if the impurity diffuses in along the entire surface, and if the diffusion time t is too short to permit the impurity to diffuse to the other side of the wafer, then the variation of impurity concentration C with distance x into the substrate is given by:

(1)C=Co+Cs−Coerfcx/2Dt1/2

where Co is the initial concentration of that impurity in the crystal and erfc is the complementary error function, tabulated in many mathematics handbooks.

High surface concentration Cs is sometimes undesirable in IC fabrication. One way of lowering it is to use a lower partial pressure of the diffusion source in the furnace. However, it is often more convenient to use a two-step process, a predeposition followed by a drive-in. The diffusion source is present during the short predeposition but not during the long drive-in step. If the product of the drive-in time td and the diffusion coefficient Dd during drive-in is much longer than that for predeposition, Dptp, and if no impurity either enters or leaves the silicon during the drive-in, then at the end the final impurity concentration at any depth is given by:

(2)C=2Cs,p/π Dptp/Ddtd1/2e−x2/4Ddt d

where Cs,p is the surface concentration during predeposition. This is a Gaussian or normal distribution of concentration with depth.

Equations (1) and (2) incorporate many assumptions that are usually not entirely true in practice. Diffusion usually takes place through holes cut in a mask, so that C depends on lateral position as well as on depth. Except for very low Cs with no oxidation, D is not constant. It varies with C, with x, with the presence of other impurities and defects, and is altered when chemical reactions such as oxidation, nitridation, and silicide formation take place at the silicon surface. In addition, some impurities segregate preferentially to the oxide while others prefer the silicon, causing large changes in Cs if oxidation is also taking place during drive-in. Consequently, numerical methods are required to predict diffusion profiles accurately. Even then, uncertainties remain so that some empirical fine-tuning of diffusion conditions is required to achieve desired concentration profiles.

Three basic diffusion mechanisms are thought to be important in silicon, although debate on the details continues. In the vacancy mechanism, a substitutional atom moves to an adjacent empty lattice site (a vacancy). Antimony diffusion in silicon is believed to occur primarily through a vacancy mechanism. In the interstitial mechanism an atom moves interstitially (in between the lattice sites). Many metallic elements such as nickel, copper, and iron are transported through silicon by interstitial diffusion. In the interstitial-kick mechanism, a substitutional atom jumps into an interstitial position, moves interstitially for some distance, and then kicks another substitutional atom off a lattice site and occupies it. Phosphorous diffusion in silicon is an example of the interstitial-kick mechanism. Substitutional impurities appear to be able to form impurity-point defect pairs which diffuse together. Some impurities, such as gold, are thought to diffuse by two mechanisms simultaneously, leading to complex behavior.

When an impurity moves by a single mechanism, the diffusion coefficient depends on temperature:

(3)D=D0exp− E/kT

where D0 is a constant, E is an activation energy, k is Boltzmann's constant, and T is the absolute temperature. Thus log D versus 1/T plots yield straight lines as shown in Fig. 7. Interstitial impurities that form no bonds with the silicon atoms, such as Li, Cu, and Fe, have the highest diffusion coefficients in Si with the least temperature dependence (least E). Interstitial atoms, such as O, that chemically bond to neighboring Si atoms, have a diffusion coefficient three to four orders of magnitude lower and a much larger E value than the interstitials, because chemical bonds must be broken before they can move. Substitutional impurities move slower still because not only must they break chemical bonds to move, but they must also move via vacancies or must kick another atom from a lattice site.

In addition to the diffusion mechanisms listed above, there are other well-known cases of enhanced diffusion mechanisms. Further discussion on the variation of diffusion rates in the presence of point defects, multiple impurities, and electric field can be found in some of the references listed at the end.

Diffused areas are characterized both electrically and chemically. Electrical characterization is performed by making resistance measurements on diffused areas. The measured resistances are then compared to standards in order to determine the amount of dopant that is electrically active. The chemical concentration of dopant may be determined by secondary ion mass spectrometry (SIMS), where a doped region is bombarded by a primary ion beam that knocks secondary ions from the doped sample. The secondary ions are then mass analyzed in order to determine the sample composition. A comparison of the electrically active and chemical concentrations is useful for investigations of dopant precipitation phenomena and for evaluation of the effect of heat treatments of dopants.

1.1.3.1. CO2–polymer interactions

Environmental concerns are driving the IC industry to introduce alternative solvent systems. In the previous section we discussed the properties of CO2 and the utilization of CO2 “snow flakes” for surface cleaning. Unlike particles and deformable organic films, the solubility of many polymeric films used in microelectronic device fabrication is limited in the various phases of CO2, except at very high pressures (above 20 MPa) [43]. Only molecules with a low solubility parameter and low polarizability such as fluoroalkyl or siloxane molecules are considered “CO2-philic” [44]. However, carbon dioxide in liquid or supercritical form diffuses into polymeric films [45–47] and causes at least one of several possible effects, including swelling, crystallization (or recrystallization), and selective extraction. Polymer swelling reduces both polymer–polymer interactions, thereby lowering the overall solubility parameter (δ) of the polymeric film, and reduces polymer–substrate interactions; as a result, debonding and subsequent polymer removal are promoted [48,49].

Pure liquid and supercritical CO2 can be considered “environmentally responsible” solvents for solvent-intensive processes in lithography such as spin coating and photoresist development. For instance, a polymer soluble in liquid CO2 can be spin coated directly using liquid CO2 [50], selectively exposed to radiation, and then developed using supercritical/liquid CO2. Supercritical CO2 has also been used to extract unreacted siloxane compounds from an organic polymer matrix [51]. In this way, processing conditions that permit 0.75 μm pattern resolution with an X-ray-exposure lithography system were established [52].

Supercritical fluid (SCF) CO2 was used to study the effect of molecular weight on the glass transition temperature and the dissolution rate of novolac resin and the subsequent effect on lithographic performance [53]. In addition to selectivity variations based on molecular weight differences, SCF CO2 is also sensitive to changes in the polarity of the polymer material; this concept has been used to design novel photoresists [54,55]. A variety of fluorine- and silicon-containing polymers were tested in both positive- and negative-tone resist schemes where the film became either more or less soluble in SCF CO2 after exposure. Recently, good contrast and excellent sensitivity of silicon-containing block copolymers has been demonstrated using SCF CO2 as a developer medium [56,57].

10.4.2 Silicon from Semiconductor Scrap

Producing semiconductor grade silicon (SEG-Si) requires a large amount of energy (450 kWh/kg). It is a principal component of solar cells, but as a result of high cost, only small amount of silicon is currently used. If the scrap silicon generated in semiconductor industry and in the conventional method of silicon manufacture is processed, and upgraded by economically viable technique, that will potentially increase the availability of high grade silicon.

A method to produce high grade silicon by electron beam (EB) heating has been developed by Yamauchi and coworkers (2004). The EB apparatus has two electron guns, a cold hearth, a water-cooled copper crucible and several sensors. Each gun has a maximum power of 200 kW. A cross section of the apparatus is shown in Figure 10.34.

About 5 kg of scrap silicon is placed on the hearth as raw material. The silicon is melted by electron beam. After exposure to a vacuum, the refined liquid silicon is poured into the carbon crucible. In the first stage melting an ingot is produced,. This is further refined by a second stage melting by electron beam. By this technique, a high grade silicon is produced. The concentration of impurities are Fe, 0.4 ppm, Cu, 0.06 ppm and Ti, 0.04 ppm. Antimony is completely removed (not detectable). This is considered to be sufficient to meet SEG-Si specifications.

14.3.1 Universal asynchronous receiver-transmitter (UART)

A UART is a microchip or integrated circuit with a hardcoded program that controls the interface between a computer or programmable controller and its attached serial devices. Specifically, it provides the computer with an RS-232-specified DTE interface so that it can “talk” to and exchange data with modems and other serial devices. UART is commonly used with RS-232 for embedded systems communications. Many microprocessor chips thus provide functionality to convert UART to RS-232 signals.

As part of this interface, the main functions of a UART include the following: (1) convert the bytes received from the computer along parallel circuits into a single-serial bit-stream for outbound transmission; (2) on inbound transmission, convert the serial bit-stream into the bytes that the computer handles; (3) add a parity bit (if it has been selected) on outbound transmissions and check the parity of incoming bytes (if selected) and discard the parity bit; (4) add start and stop delineators on outbound data and strip them from inbound transmissions; (5) handle interrupts from serial devices with special ports such as keyboard and mouse; (6) possibly handle other kinds of interrupt and device management that require coordinating the computer’s speed of operation with device speeds.

Figure 14.15 is a schematic diagram of a UART microchip, which usually contains the following components: (1) transmit and receive buffer, (2) transmit and receive register, (3) data bus buffer, (4) control logics, and (5) clock circuit. The control logic circuitry of UART has a number of internal registers that contain all the relevant status information for the device. These registers are generally mapped onto the computer’s memory and can be accessed from the main CPU. The key is that each UART contains a shift register that is the fundamental method of conversion between serial and parallel forms.

The word asynchronous indicates that a UART recovers character timing information from the data stream, using designated start and stop bits to indicate the framing of each character. By convention, teletype-style UARTs send a start bit, 5–8 data bits, least-significant-bit first, an optional parity bit, and then a stop bit. The start bit is the opposite polarity of the data-line’s normal state. The stop-bit is the data-line’s normal state, and provides a space before the next character can start. In mechanical teletypes, the stop bit was often stretched to two bit times to give the mechanism more time to finish printing a character. A stretched stop bit also helps resynchronization. The parity bit can either make the number of bits odd or even, or it can be omitted. Odd parity is more reliable because it ensures that there will always be a data transition, and this permits many UARTs to resynchronize.

As shown in Figure 14.15, most UARTs are designed to assert an interrupt line when data have been received. This enables the CPU to run an interrupt service routine that removes data from the volatile registers and buffers in the UART and places them into a more stable area of general-purpose computer memory.